Field-programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) have been used in data communication and telecommunication systems. Conventional PLDs and FPGAs consist of an array of programmable elements, with the elements programmed to implement a fixed function or equation. Some currently-available Complex PLD (CPLD) products may comprise arrays of logic cells.
One of the drawbacks of conventional FPGA, PLD, and CPLD devices is the limited processing resources. For example, the area of such devices is typically dominated by the routing resources, which may consume up to 80-90% of the total area. Due to the ever-increasing design complexity, various Electronic Design Automation (EDA) programs (tools) use iterative processes to ensure that the processing resources of a target device are efficiently utilized when a design is placed and routed on the device.
Because of the increased design complexity and the iterative nature of the design process, the predictability of a design tool becomes a key issue in the placement and routing of an electronic design on a target device. In this regard, high variance in post-routing delays poses a serious threat to meeting timing constraints in Engineering Change Order (ECO) scenarios. For example, after a design is mapped to a target device and timing constraints are met, a minor ECO-type change may make the design fail timing constraints due to high variance in post-routing delays. By way of illustration, a minor ECO-type change in the pin placement, a perturbation in the initial instance order, or a delta change in the choice of a starting solution during annealing may drastically change the quality of routing (QoR) and may lead to costly and time-consuming design iterations.